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uart
- this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
miaobiao
- 用VERILOG实现秒表的开发设计，(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理；(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发；(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface c
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
fir
- 用状态机编写的FIR，verilog代码，已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
Automachine_project
- verilog 语言写的自动售货机程序，系IC课程设计代码，QUARTUS -verilog language written in a vending machine program, the Department of IC curriculum design code, QUARTUS II
AutoWashing
- 基于verilog-hdl的洗衣机自动控制电路，经下载仿真测试通过 附带时钟分频器-Verilog-hdl-based automatic control circuit of the washing machine, after download the simulation test
vending
- vending machine for Quartus 8.1 version. verilog , vhdl code
seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
uartverilog
- Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
moore
- moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
state
- verilog语言编写的高效状态机设计，值得好好学习一下-verilog language efficient state machine design, it is well to study the
uart
- verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
RS232
- It s combination logic for UART. Edited in verilog-HDL.
thunderbird
- 控制左右两对灯一次点亮，用状态机实现，verolog语言编写-Control about two lit the lamp again with the state machine implementation, verolog language
dct01
- Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
Verilog-Vending-Machine-_-georgeBlog_-A-blab-on-t
- using vending machine we can collect ice cream along with a change or can be fullfilled by any other subsequent cooldrinks
verilog
- 介绍了一种硬件控制的自动数据采集系统的设计方法，包括数字系统自顶向下 (1DP—DOwN)的设计思路，Vernog}Ⅱ)L对系统硬件的描述和状态机的设计-Introduced a hardware-controlled automated data acquisition system design, including digital systems from top to bottom (1DP-DOwN) design ideas, Vernog} Ⅱ) L of the system
verilog
- 用verilog语言进行状态机的时序与功能仿真-Verilog state machine language with timing and functional simulation
dir3
- VERILOG 语言写的使用状态机实现奇数分频-VERILOG language is written by the state machine to implement an odd number of points frequency